1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to improvements of a circuit for error checking/correction and a circuit for generating a code word which can check/correct an error, comprised in a large capacity semiconductor memory device having error checking/correcting functions.
2. Description of the Background Art
As a semiconductor memory device such as EEPROM (an electrically writable and erasable non-volatile semiconductor device), DRAM (a dynamic random access memory) or SRAM (a static random access memory) has its capacity increased, the number of defective memory cells increases, and therefore it is considered that a conventional redundancy memory cell system cannot cope with such a situation. Further, it sometimes occurs during the operation of a semiconductor memory device that erroneous data are written in or read out due to latent defective cells which were not detected when the device was put on the market, noises and the like. Accordingly, the error checking and correcting functions of data have been recently added to a large capacity semiconductor memory device. First of all, a method of error checking/correcting of information will be described taking as an example Hamming code which is one of the linear codes commonly used.
First, a two-dimensional block code of a length n is considered. A code which regards as a code word all the series w=(x1,x2, . . . , x.sub.n) satisfying the following linear simultaneous equations is called a linear code. ##EQU1##
a.sub.ij (i=1, . . . , n:j=1, . . . , n) is assumed to be a constant having 0 or 1, and an operation thereof is to be performed following Boolean algebra.
The above simultaneous equation is called a parity check equation, while the coefficient matrix of this parity check equation shown below is called a parity check matrix. ##EQU2##
In the parity check equation, variables which can be independently selected are called information bits, while variables to be determined according to the selected variables are called check bits.
Assuming a code is w, the parity check equation is expressed as follows. EQU Hw.sup.T =0 (mod. 2)
Where, w is the above described code word, while T is a symbol representing transposition.
In the above described parity check matrix, the one taking the following form is particularly called a canonical parity check matrix. ##STR1## Where I.sub.m is a unit matrix of m.times.m.
Here, the check bits comprise the first m bits (x1, x2, . . . , x.sub.m). The relation between the information bits and the check bits in the case of the canonical parity check matrix is given in the following expression. EQU (x1 . . . x.sub.m)=(x.sub.m+1, . . . , x.sub.n) P.sup.T (mod. 2)
Therefore, when information bits (x.sub.m+1, . . . , x.sub.n) are arbitrarily selected, the check bits corresponding thereto are uniquely determined.
Corresponding to the above described canonical parity check matrix, the matrix shown below is called a generation matrix. ##STR2##
For the linear code, a code word w is generated from the contents of the information bit w.sub.1 by employing the generation matrix G as follows. EQU w=w.sub.1 G (mod. 2)
In the above parity check matrix H, when each column is non-0, and, no columns exist which are equal to each other, a code generated by the generation matrix G associated with the matrix H is called a Hamming code or a single error correction code of Hamming.
For the code word w,
s=Hw.sup.T (mod. 2) is called a syndrome "s" of the w. Since the syndrome s is 0 for an error-free code word w, if the syndrome s of a given code word is not 0, the code word includes an error. When the given code word includes a single error pattern as expressed below, ##EQU3## the syndrome s is EQU s=H (w+e.sub.i).sup.T =He.sub.i.sup.T.
Namely, the syndrome s is equal to the i-th column of the parity check matrix H.
When the given code word is a Hamming code, each column of the check matrix H is non-0, and no columns exist which are equal to each other, so that information having a single error pattern has a syndrome s differing from each other. Accordingly, error checking and correction can be carried out by obtaining the syndrome of the given data and by adding the single error pattern corresponding thereto to the given information.
Correct data writing/reading in the semiconductor memory device is carried out by employing the above described code word which can correct/check an error. That is, in data writing, check bits are generated for the data externally given, and then, the check bits generated for the given write-in data are linked to the write-in data to be stored. In data reading, accessed memory cell information and the check bits linked thereto are both read to be a code word, and the error checking and correction based on the code word is carried out, thereby carrying out correct data reading. The configuration and operation of the semiconductor memory device having error checking/correcting functions according to the above described theory will now be described as follows.
FIG. 1 is a diagram illustrating the entire schematic configuration of a conventional semiconductor memory device having an error correcting function. Referring to FIG. 1, the conventional semiconductor memory device comprises a memory cell array 1 for storing information which is externally provided (hereinafter referred to as information bits), and a memory cell array 2 for checking which comprises a plurality of memory cells for storing checking information generated corresponding to the information bits of the memory cell array 1 (hereinafter referred to as check bits). The memory cell array 1 comprises the memory cells arranged in a plurality of rows and columns. The memory cell array for checking comprises a plurality of memory cells as well.
In order to select the memory cells of the memory cell array 1, there are provided an X decoder 3 for decoding an X address provided via X address input terminals 21a-21m to generate a row selecting signal, and a Y decoder 4 for decoding a Y address provided via Y address input terminals 22a-22n to generate a column selecting signal. The row and column selecting signals from the X decoder 3 and the Y decoder 4 are also supplied to the memory cell array 2 for checking.
Furthermore, there are provided a data input and output circuit 6 for inputting data into and outputting it from an external device via data terminals 23a-23i in order to input and output the data, an error correction coding circuit 7 for receiving the information bits provided via the data input and output circuit 6 to generate the check bits according to a predetermined generation matrix, thereby adding the generated check bits to the provided information bits to pass them together, a writing/reading circuit 5 for writing the information bits from the error correction coding circuit 7 into the selected memory cells in the memory cell array 1 and also writing the check bits into the selected memory cells in the memory cell array 2 for checking, and for reading the information bits and check bits from the memory cells which are selected in data reading, and an error decoding circuit 8 for receiving the information bits and check bits provided from the writing/reading circuit 5 to check and correct an error of the read-out data (information bits and check bits) and then subsequently for providing the information bits (which are corrected) to the data terminals 23a-23i via the data input and output circuit 6. This semiconductor memory device is integrated onto a semiconductor chip 100.
Now, the operation of the semiconductor memory device having a x2 configuration, i.e. the configuration in which data are input or output in a 2-bit unit, will be described as an example. Further, the following matrix is considered as a generation matrix G employed in the error correction coding circuit 7. ##EQU4##
The following matrix is then considered as a check matrix H employed in the error decoding circuit 8. ##EQU5##
In the above configuration, assuming that the information bits externally provided are D0, D1, while the check bits generated depending on the information bits are P1, P2, P3, a code word w capable of error checking and correcting is given as follows. EQU w=(D0, D1, P1, P2, P3) EQU =(D0, D1)G ##EQU6##
In the operation of the error decoding circuit 8 in accordance with the above described check matrix H, a syndrome s is generated from the read code word (a combination of information bits and check bits) following the expression below. EQU s=(S.sub.0, S.sub.1, S.sub.2)=Hw.sup.T ##EQU7##
When the syndrome s is not 0, it is identical to a column vector of the check matrix H. Therefore, error correction is carried out by checking which column vector in the check matrix H is equal to this syndrome and by inverting a bit value of the column corresponding to this column vector.
A relation between input and output of the above described coding and decoding is illustrated in FIG. 2. The operations of the data write-in and read-out of the conventional semiconductor memory device will be described hereinafter with reference to FIGS. 1 and 2.
The case in which 2-bit data (0, 1) are externally supplied via the data terminals 23a-23i is now considered. The external data (a code word) are transmitted to the error correction coding circuit 7 after waveform-shaped in the input and output circuit 6. The error correction coding circuit 7 generates check bits (1, 1, 0) from supplied information bits (0, 1) according to the above generation matrix G and adds the generated check bits to the supplied information bits to provide them to the writing/reading circuit 5. On the other hand, the X address and the Y address are respectively supplied to the X decoder 3 and the Y decoder 4 via the X address input terminals 21a-21m and the Y address input terminals 22a-22n. The X decoder 3 and the Y decoder 4 both decode the provided address to select their corresponding row and columns from the memory cell array 1 and the memory cell array 2 for checking. The information bits from the writing/reading circuit 5 are written in the selected memory cells of the memory cell array 1, while the check bits are written in the selected memory cells of the memory cell array 2 for checking. Accordingly, the information bits and the check bits are linked with each other to be stored in the memory cell array 1 and the memory cell array 2 for checking.
The reading operation will now be described. The X address and the Y address are supplied to the X decoder 3 and the Y decoder 4 via the address input terminals 21a-21m and 22a-22n, respectively. The X decoder 3 and the Y decoder 4 decode the supplied addresses to select their corresponding memory cells in the memory cell array 1 and the memory cell array 2 for checking. As a result, the information bits are read from the selected memory cells of the memory cell array 1, while the check bits are read from the memory cell array 2 for checking. The read-out information bits and check bits are supplied to the writing/reading circuit 5 and then to the error decoding circuit 8. The error decoding circuit 8 carries out the error checking and correction of the information bits and check bits from the supplied information bits and check bits in accordance with a table shown in FIG. 2. The case in which the read information bits are (0, 1) and the check bits are (1, 1, 0) is now considered. In such a case, no error exists in the read code word (information bits and check bits), so that the information bits (0, 1) are output from the error decoding circuit 8 so as to be transmitted to the outside of the device via the data input and output circuit 6 and the data terminals 23a-23i.
The case in which the information bits to be read (0, 1) are actually read (0, 0) in 1-bit error, due to a certain defect in the memory cells, noises or the like, will now be considered. In this case, since the check bits which are linked to the information bits to be stored and read out are (1, 1, 0), the error correction decoding circuit 8 corrects the read-out data (0, 0) to (0, 1) and then supplies them to the data input and output circuit 6 as shown in FIG. 2. In the case in which 1-bit error occurs only in the check bits from the memory cell array 2 for checking as well, no error exists in the information bits (0, 1) as shown in FIG. 2, so that the read information bits (0, 1) are supplied to the data input and output circuit 6 via the error decoding circuit 8.
As has been described, correct data reading can be carried out, and it can also be carried out even in the case that the data are read which are different from the originally written data due to some causes (the defects in a memory cell, noises etc.)
As mentioned above, the conventional semiconductor memory device having the error correcting function allows occurrence of the check bits and addition of the check bits to information bits according to the predetermined generation matrix and check matrix, for error checking and correction in the read-out code word (information bits and check bits). Therefore, if the information bits externally provided are established, the check bits added corresponding thereto are uniquely determined. And also a read code word, the data to be output from the error decoding circuit 8 are uniquely determined according to the check matrix. Therefore, the error correction coding circuit 7 and the error decoding circuit 8 are implemented on a hardware basis employing logic gates in the conventional semiconductor memory device. The detailed configurations of the error correction coding circuit and the error decoding circuit will then be described.
FIG. 3 is a diagram illustrating the detailed configurations of the error correction coding circuit and the error decoding circuit in a logic level when the semiconductor memory device inputs and outputs data in a 2-bit unit. Referring to FIG. 3, the error correction coding circuit 7 comprises an XOR gate X1 for receiving information bits D0, D1 externally provided, a signal line S1 for passing the information bit D0 externally provided, and a signal line S2 for passing the information bit D1 externally provided. An XOR gate Xl output provides a check bit P1, and the signal line S1 supplies a check bit P2 while the signal line S2 applies a check bit P3.
The error decoding circuit 8 comprises five XOR gates X2-X6, two inverters I1, I2, and two AND gates A1, A2. The XOR gate X2 receives the information bits D0, D1 from the memory cell array 1 and the check bit P1 from the memory cell array 2 for checking. The XOR gate X3 receives the information bit D1 and the check bit P2. The XOR gate X4 receives the information bit D1 and the check bit P3. The inverter I1 receives the XOR gate X3 output. The inverter I2 receives the XOR gate X4 output. The AND gate A1 receives the XOR gate X2 output, the XOR gate X3 output and the inverter I2 output. The AND gate A2 receives the XOR gate X2 output, the inverter I1 output and the XOR gate X4 output. The XOR gate X5 receives the information bit D0 and the AND gate A1 output. The XOR gate X6 receives the information bit D1 and the AND gate A2 output. The corrected information bits D0, D1 through the XOR gates X5, X6, ie. are to be supplied to the data input and output circuit 6. By implementing the error correction coding circuit and error decoding circuit on a hardware basis as described above, error checking and correction can be carried out more rapidly than on a software basis.
However, when a circuit for an error checking/correcting code is configured on a hardware basis as has been described, it includes a number of logic gates, so that when an operating supply potential thereof fluctuates, the potential level of each logic gate output fluctuates. Accordingly, a problem arises that the speed of logic operation on the data decreases and an erroneous logical operation is also carried out. This problem will be described in detail with reference to FIG. 4.
Referring to FIG. 4, the XOR gate Xl included in the error correction coding circuit comprises a CMOS inverter stage formed of a p channel MOS transistor T1 and an n channel MOS transistor T2, and a CMOS inverter stage formed of a p channel MOS transistor T3 and an n channel MOS transistor T4. The inverter stage formed of the transistors T1, T2 receives the information bit D0. The inverter stage formed of the transistors T3, T4 receives the information bit D1. Further, the XOR gate X1 comprises a pass transistor T5 which is turned on responsive to the output of the inverter stage formed of the transistors T3, T4 so as to pass the output of inverter stage formed of the transistors T1, T2, a pass transistor T6 which is turned on responsive to the output of inverter stage formed of the transistors T3, T4 so as to pass the information bit D0, a pass transistor T7 which is turned on responsive to the information bit D1 so as to pass the output of the inverter stage formed of the transistors T1, T2, a pass transistor T8 which is turned on responsive to the information bit D1 output so as to pass the information bit D0, and an inverter I3 for inverting the output of the pass transistor T8 to be output.
Similarly, the error decoding circuit 8 comprises a logic gate formed of MOS transistors. The XOR gate X2 comprises a CMOS inverter stage formed of the transistors T10, T11, a CMOS inverter stage formed of the transistors T12, T13, a CMOS inverter stage formed of the transistors T14, T15, and pass transistors T16-T23. The inverter stage formed of the transistors T10, T11 receives the check bit P1. The inverter stage formed of the transistors T12, T13 receives the information bit D0. The inverter stage formed of the transistors T14, T15 receives the information bit D1. The pass transistors T16, T17 are turned on responsive to the output of the inverter stage formed of the transistors T12, T13. The pass transistors T18, T19 are turned on responsive to the information bit D0. The pass transistors T20, T21 are turned on responsive to the output of the inverter stage formed of the transistors T14, T15. The pass transistors T22, T23 are turned on responsive to the information bit D1. The output of the XOR gate X2 is output via the inverter I4.
The XOR gate X4 comprises a CMOS inverter stage formed of the transistors T40, T41, pass transistors T42, T43 which are turned on responsive to the output of the inverter stage formed of the transistors T14, T15, pass transistors T44, T45 which are turned on responsive to the information bit D1, an inverter 16 provided in an output portion.
The inverter I1 comprises a CMOS inverter formed of the transistors T50, T51.
The inverter I2 comprises a CMOS inverter formed of the transistors T52, T53.
The AND gate A1 comprises input transistors T60, T61 and T62, load transistors T63, T64 and T65, a CMOS inverter stage formed of MOS transistors T66, T67 provided at the output portion.
The AND gate A2 comprises input transistors T71, T72 and T73, load transistors T74, T75 and T76, and an inverter stage formed of the transistors T77, T78 in the output portion.
The XOR gate X5 comprises a CMOS inverter stage formed of the transistors T80, T81, an inverter I7 for receiving the output of the AND gate A1, pass transistors T82, T83 which are turned on responsive to the output of the inverter I7, pass transistors T84, T85 which are turned on responsive to the output of the AND gate A1, and an inverter I8 provided at the output stage. The corrected information bit D0 is output from the inverter I8.
The XOR gate X6 comprises a CMOS inverter stage formed of the transistors T90, T91, an inverter stage I9 for receiving the output of the AND gate A2, pass transistors T92, T93 which are turned on responsive to the output of the inverter I9, pass transistors T94, T95 which are turned on responsive to the output of the AND gate A2, and an inverter I10 provided at the output stage. The corrected information bit D1 is output from the inverter I10.
Sense amplifiers 9 for sensing and amplifying the read-out information are provided between the memory cell array 1 for information bits and the memory cell array 2 for check bits, and the error coding circuit.
An operating margin on the high potential side of the semiconductor memory device is usually specified as 4V to 6V, for example. The operating margins on the high potential sides of the memory cell arrays 1, 2 are set at 3V to 7V larger than the operating margin of this semiconductor memory device. However, since the operating margins of the high potential sides of the error correction coding circuit and the error decoding circuit are narrow at 4V to 6V, the entire operating margin on the high potential side of the semiconductor memory device is determined by the high potential side operating margin of this error correcting circuit configuration.
The case that the operation supply potential V.sub.cc is lowered from 5V to 4V for some reason is now considered, for example. In this case, each XOR gate includes inverter stages, and pass transistors controlled responsive to the output of the inverter stages. Therefore, if the operation supply potential V.sub.cc is lowered to 4V, for example, the "H" level of the inverter stage output is lowered, as the inverter stage output level applied to the gate of each pass transistor is also lowered. Each pass transistor can only transmit a voltage equal to the difference between the voltage applied to each gate and each inherent threshold voltage. Therefore, a signal potential transmitted from the pass transistor is made further lower than 4V by the threshold voltage of this transistor. Since a plurality of stages of such pass transistor are provided, the output of the pass transistor on the output side of each XOR gate is further lowered. The lowered potential level of this output signal is further transmitted in the decoding circuit through the inverter stages and the pass transistors, so that the potential level of this signal is further lowered. The operation rate in each logic gate is reduced due to the lowering of the potential level of this signal. As for the operation rate in the inverter stage for example, the higher the supply potential is, the greater the charging rate of the output thereof is, so that an access rate is increased; on the other hand, the lower supply potential reduces the charging at the output of the inverter, so that the access rate is decreased. Furthermore, it is considered that when an input potential applied to each logic gate reaches near an input logic threshold thereof, each logic gate cannot carry out a correct logical operation, thereby transmitting an erroneous signal level as an output signal.
Therefore, despite the provision of the circuitry for correcting the error of the data in the memory device as described above, some disadvantages arise that the operating margin on the lowered potential side of the circuitry for error checking/correcting is narrow, so that the correct decision and correction of the data cannot be carried out, and/or the decision operation thereof proceeds slower.
Namely, when the circuitry for checking and correcting the error of information is implemented on a hardware basis employing the logic gates, the disadvantages arise that the operating margin on the lowered potential side in the semiconductor memory device is narrowed, and the correct error checking/correction of information cannot be carried out, and/or that the decision operation thereof proceeds slower, so that the access time of the semiconductor memory device is reduced.
In a computer system, the configuration in which a circuit for error checking/correction provided external to a main memory is formed in a ROM implementation, is disclosed in Japanese Patent Laying-Open No. 61-101857. It is an object of this prior art to reduce the amount of hardware when circuits for error checking/correction, i.e. a check bit generating circuit and an error checking/correcting circuit, are formed of logic gates such as XOR gates, AND gates etc. For this purpose, the check bit generating circuit and the error checking/correcting circuit are formed employing a ROM "which is commonly and widely used and is available at a low cost". Accordingly, this prior art only intends to improve an error checking/correcting-dedicated circuit provided external to the memory device, but not a circuit for error checking/correction included in the semiconductor memory device, and further, it recognizes none of the problems inherent to the semiconductor memory device having the above described error checking/correcting functions.